philips semiconductors product specification 74abt2953 octal registered transceiver, inverting (3-state) 1 1995 sep 06 853-1555 15702 features ? 8-bit registered transceiver ? independent registers for a and b buses ? output capability: +64ma/32ma ? latch-up protection exceeds 500ma per jedec std 17 ? esd protection exceeds 2000v per mil std 883 method 3015 and 200v per machine model ? live insertion/extraction permitted ? power-up 3-state ? power-up reset description the 74abt2953 high-performance bicmos device combines low static and dynamic power dissipation with high speed and high output drive. the 74abt2953 device is an 8-bit registered inverting transceiver. two 8-bit back-to-back registers store data flowing in both directions between two bidirectional buses. data applied to the inputs is entered and stored on the rising edge of the clock (cpxx) provided that the clock enable (cexx ) is low. the data is then present at the 3-state output buffers, but is only accessible when the output enable (oexx ) is low. data flow from a inputs to b outputs is the same as for b inputs to a outputs. quick reference data symbol parameter conditions t amb = 25 c; gnd = 0v typical unit t plh t phl propagation delay cpba to a n or cpab to b n c l = 50pf; v cc = 5v 5.0 ns c in input capacitance v i = 0v or v cc 4 pf c i/o i/o capacitance outputs disabled; v o = 0v or v cc 7 pf i ccz total supply current outputs disabled; v cc =5.5v 500 na ordering information packages temperature range outside north america north america dwg number 24-pin plastic dip 40 c to +85 c 74abt9253 n 74abt2953 n sot222-1 24-pin plastic so 40 c to +85 c 74abt2953 d 74abt2953 d sot137-1 24-pin plastic ssop type ii 40 c to +85 c 74abt2953 db 74abt2953 db sot340-1 24-pin plastic tssop type i 40 c to +85 c 74abt2953 pw 74abt2953pw dh sot355-1 pin configuration 1 2 3 4 5 6 7 8 9 10 15 16 17 18 19 20 21 22 23 24 b7 b6 b5 b4 b3 b2 b1 b0 oeab a0 cpab a1 a2 a3 a4 a5 a6 a7 v cc oeba 11 14 ceab cpba 12 13 gnd ceba top view sa00305 pin description pin number symbol name and function 10, 14 cpab / cpba clock input a to b / clock input b to a 11, 13 ceab / ceba clock enable input a to b / clock enable input b to a 16, 17, 18, 19, 20, 21, 22, 23 a0 a7 data inputs/outputs (a side) 1, 2, 3, 4, 5, 6, 7, 8 b0 b7 data outputs/outputs (b side) 9, 15 oeab / oeba output enable inputs 12 gnd ground (0v) 24 v cc positive supply voltage
philips semiconductors product specification 74abt2953 octal registered transceiver, inverting (3-state) 1995 sep 06 2 logic symbol 16 17 18 19 20 21 22 23 a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 8765 432 1 15 9 10 14 11 13 cpab cpba ceab ceba oeba oeab sa00306 logic symbol (ieee/iec) c6 1, 4, 5 14 16 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 2, 3, 6 c5 10 en4 9 en3 15 en2 13 en1 11 sa00307 function table for register an or bn inputs internal operating an or bn cpxx cexx q mode x x h nc hold data l h l l l h load data h = high voltage level l = low voltage level = low-to-high transition x = don't care xx = ab or ba nc= no change function table for output enable inputs internal an or bn operating oexx q outputs mode h x z disable outputs l l l h h l enable outputs h = high voltage level l = low voltage level x = don't care xx = ab or ba z = high impedance ooffo state absolute maximum ratings 1, 2 symbol parameter conditions rating unit v cc dc supply voltage 0.5 to +7.0 v i ik dc input diode current v i < 0 18 ma v i dc input voltage 3 1.2 to +7.0 v i ok dc output diode current v o < 0 50 ma v out dc output voltage 3 output in off or high state 0.5 to +5.5 v i out dc output current output in low state 128 ma t stg storage temperature range 65 to 150 c notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditionso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not exceed 150 c. 3. the input and output voltage ratings may be exceeded if the input and output current ratings are observed.
philips semiconductors product specification 74abt2953 octal registered transceiver, inverting (3-state) 1995 sep 06 3 logic diagram ceab ce q cp d ce q cp d detail a detail a x 7 cpab oeab a 0 cpba oeba b 0 ceba 8 7 6 5 4 3 2 1 11 10 9 16 17 18 14 15 19 20 21 22 23 13 a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 1 b 2 b 3 b 4 b 5 b 6 b 7 sa00308
philips semiconductors product specification 74abt2953 octal registered transceiver, inverting (3-state) 1995 sep 06 4 recommended operating conditions symbol parameter limits unit min max v cc dc supply voltage 4.5 5.5 v v i input voltage 0 v cc v v ih high-level input voltage 2.0 v v il low-level input voltage 0.8 v i oh high-level output current 32 ma i ol low-level output current 64 ma d t/ d v input transition rise or fall rate 0 10 ns/v t amb operating free-air temperature range 40 +85 c dc electrical characteristics limits symbol parameter test conditions t amb = +25 c t amb = 40 c to +85 c unit min typ max min max v ik input clamp voltage v cc = 4.5v; i ik = 18ma 0.9 1.2 1.2 v v cc = 4.5v; i oh = 3ma; v i = v il or v ih 2.5 3.2 2.5 v v oh high-level output voltage v cc = 5.0v; i oh = 3ma; v i = v il or v ih 3.0 3.7 3.0 v v cc = 4.5v; i oh = 32ma; v i = v il or v ih 2.0 2.3 2.0 v v ol low-level output voltage v cc = 4.5v; i ol = 64ma; v i = v il or v ih 0.42 0.55 0.55 v v rst power-up output low voltage 3 v cc = 5.5v; i o = 1ma; v i = gnd or v cc 0.13 0.55 0.55 v i i input leakage control pins v cc = 5.5v; v i = gnd or 5.5v 0.01 1.0 1.0 m a current data pins v cc = 5.5v; v i = gnd or 5.5v 5 100 100 m a i off power-off leakage current v cc = 0.0v; v o or v i 4.5v 5.0 100 100 m a i pu / ipd power-up/down 3-state output current 4 v cc = 2.1v; v o = 0.5v; v i = gnd or v cc ; v oe = don't care 5.0 50 50 m a i ozh 3-state output high current v cc = 5.5v; v o = 2.7v; v i = v il or v ih 5.0 50 50 m a i ozl 3-state output low current v cc = 5.5v; v o = 0.5v; v i = v il or v ih 5.0 50 50 m a i cex output high leakage current v cc = 5.5v; v o = 5.5v; v i = gnd or v cc 5.0 50 50 m a i o output current 1 v cc = 5.5v; v o = 2.5v 50 65 180 50 180 ma i cch v cc = 5.5v; outputs high, v i = gnd or v cc 110 250 250 m a i ccl quiescent supply current v cc = 5.5v; outputs low, v i = gnd or v cc 20 30 30 ma i ccz v cc = 5.5v; outputs 3-state; v i = gnd or v cc 110 250 250 m a d i cc additional supply current per input pin 2 v cc = 5.5v; one input at 3.4v, other inputs at v cc or gnd 0.3 1.5 1.5 ma notes: 1. not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. this is the increase in supply current for each input at 3.4v. 3. for valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. this parameter is valid for any v cc between 0v and 2.1v, with a transition time of up to 10msec. from v cc = 2.1v to v cc = 5v 10% a transition time of up to 100 m sec is permitted.
philips semiconductors product specification 74abt2953 octal registered transceiver, inverting (3-state) 1995 sep 06 5 ac characteristics gnd = 0v; t r = t f = 2.5ns; c l = 50pf, r l = 500 w limits symbol parameter waveform t amb = +25 c v cc = +5.0v t amb = 40 c to +85 c v cc = +5.0v 0.5v unit min typ max min max f max maximum clock frequency 1 150 200 150 mhz t plh t phl propagation delay cpba to an, cpab to bn 1 2.0 2.5 5.1 5.7 6.6 7.2 2.0 2.5 7.6 8.2 ns t pzh t pzl output enable time oeba to an, oeab to bn 3 4 1.0 2.2 4.0 5.3 4.8 6.2 1.0 2.2 5.8 7.5 ns t phz t plz output disable time oeba to an, oeab to bn 3 4 2.0 1.5 6.1 5.6 7.6 7.1 2.0 1.5 8.1 7.6 ns ac setup requirements limits symbol parameter waveform t amb = +25 c v cc = +5.0v t amb = 40 c to +85 c v cc = +5.0v 0.5v unit min typ min t s (h) t s (l) setup time an to cpab or bn to cpba 2 4.0 3.0 2.5 1.1 4.0 3.0 ns t h (h) t h (l) hold time an to cpab or bn to cpba 2 0.0 0.0 1.0 2.0 0.0 0.0 ns t s (h) t s (l) setup time ceab to cpab, ceba to cpba 2 3.5 2.5 2.0 0.9 3.5 2.5 ns t h (h) t h (l) hold time ceab to cpab, ceba to cpba 2 0.0 0.0 0.5 1.0 0.0 0.0 ns t w (h) t w (l) cpab or cpba pulse width, high or low 1 3.0 3.5 2.0 1.1 3.0 3.5 ns ac waveforms v m = 1.5v, v in = gnd to 3.0v v m v m v m v m v m 1/f max t w (h) t w (l) t phl t plh cpba or cpab an or bn sa00087 waveform 1. propagation delay, clock input to output, clock pulse width, and maximum clock frequency oeab, oeba v m t pzh t phz 0v v oh 0.3v an, bn v m v m sa00310 waveform 3. 3-state output enable time to high level and output disable time from high level v m an, bn ceab , ceba v m v m v m v m v m cpab, cpba t s (h) t h (h) t s (l) t h (l) sa00309 waveform 2. data setup and hold times oeab , oeba t pzl t plz 0v v ol +0.3v an, bn v m v m v m sa00311 waveform 4. 3-state output enable time to low level and output disable time from low level
philips semiconductors product specification 74abt2953 octal registered transceiver, inverting (3-state) 1995 sep 06 6 test circuit and waveforms pulse generator r t v in v out c l r l v cc r l 7.0v test circuit for 3-state outputs v m v m t w amp (v) negative pulse 10% 10% 90% 90% 0v v m v m t w amp (v) positive pulse 90% 90% 10% 10% 0v t thl (t f ) t tlh (t r )t thl (t f ) t tlh (t r ) v m = 1.5v input pulse definition definitions r l = load resistor; see ac characteristics for value. c l = load capacitance includes jig and probe capacitance; see ac characteristics for value. r t = termination resistance should be equal to z out of pulse generators. input pulse requirements family amplitude rep. rate t w t r t f 74abt 3.0v 1mhz 500ns 2.5ns 2.5ns switch position test switch t plz closed t pzl closed all other open sa00012 d.u.t.
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